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Altera_Forum
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15 years ago

Turn off enable_advanced_io_timing for Arria II GX?

I got forced into an Arria II GX due to lack of resources in an Arria GX. I was, with the Arria GX, able to assign the pin loading for each pin in my SO-DIMM interface. The Arria II GX forces me to d...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Okay, I have figured out that I can add in the far-end load capacitance per pin for my SO-DIMM interface. Once I have the actual distributed L/C of the traces (from Hyperlynx after layout) I will update the board trace models in the pin planner.

I am however not quite clear how the near-end pin capacitance is modeled. My bidir DQ pins are shown in the board trace model edit screen as output pins (see attached screen shot). Should I just add the Arria II DQ pin capacitance in the Cn text box and ignore that the graphics shows the driver/receiver in the wrong direction?

Thanks.