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JPrig's avatar
JPrig
Icon for New Contributor rankNew Contributor
4 years ago

TTK fails to run on Arria 10

Hi, I try to get TTK up and running on a custom Arria 10 design. My FPGA project is very simple. I have a PLL which generates a system clock of 120MHz and a reset synchronized to this clock. I use...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

HI,


From the error message, it's basically complain about either your didn't provide reconfig_clk from your board or the transceiver is not release from reset properly.

  • Can you double check your reconfig_clk (100MHz to 125MHz) and verify your transceiver power up sequence to ensure calibration is done and both PCS Tx_ready and Rx_ready signal are asserted ?
  • Pls share with me your signal_tap file where you captured all the transceiver status signals from Transceiver PHY reset controller IP
  • Another thing to watch out is did you provide clock frequency to FPGA clkusr pin as transceiver power up calibration clock ?
  • other suggestion is pls reduce/disable your JTAG connection chain on board and also reduce the JTAG clock frequency from 24MHz to maybe 16MHz or 6MHz to see if it helps


Thanks.


Regards,

dlim