tse_sgmii_lvds_altera_lvds_core20_141_..sdc: -1 could not be matched with with a port

Hello,

In our Arria10 FPGA design we are implementing the Triple-Speed-Ethernet ip block. This ip block needs a REFCLK of 125MHz.

Ideally I want to connect this refclk to a PLL output. This PLL is an Altera IOPLL.

After generating and connecting the Altera IOPLL and the TSE ip blocks (using the IP catalog in Quartus v14.1), I'm facing problems in TimeQuest, hold- and setup timing issues related to this REFCLK.

After studying the compilation report, I found out that the REFCLK (is output of my PLL) is not found:

Warning (332174): Ignored filter at ip_arria10_tse_sgmii_lvds_altera_lvds_core20_141_vxotqby.sdc(123): -1 could not be matched with a port

This line 123 in the sdc file: set ref_ck_pin [get_port_info -name $ref_ck_port_id]

Interesting to know when I'm not using the PLL (connect REFCLK to a real FPGA pin), there are no timing issues.

Do you have a suggestion how to make it working with the PLL? How to make the Fitter find the right clock so that the warning goes away?

thanks,

Leon