There are several problems here. I would suggest to read a book or an online course on VHDL first.
use IEEE.STD_LOGIC_SIGNED;
use IEEE.STD_LOGIC_UNSIGNED;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
please don't do that. The non standard std_logic_signed and std_logic_unsigned cause many problems, especially when used at the same time than numeric_std. If you include both it is even worse because the operators on std_logic_vector are overloaded for both signed and unsigned operations. There is no way to know what will happen. Please only include std_logic_1164 and numeric_std
variable count:std_logic_vector(2 downto 0) := "000";
as you are using numeric_std, you can declare this variable as an unsigned instead of std_logic_vector, and that way you can use the + and - operators on it.
count := DIN;
once you change count to the unsigned type, this line won't work any more because count and DIN are different types. Either change the DIN port to also be an unsigned, or do an explicit cast:
count := unsigned(DIN);
count := "count+1 >";
there are several syntax errors there. I don't know where the '>' is coming from, and the quotes "" are only used to specify a literal value. If you just want to increase the counter, do
count := count+1;
Your code doesn't do anything yet when the counter reaches its final value.