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Honored Contributor
Honored ContributorTrying to generate a signal.
Hello :) I am really new with VHDL, I am doing my thesis coding in it, and I am stuck in some parts, so maybe someone could help me? I have created an optimized 4x4 bits multiplier, and i...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- "rising_edge type specified in Qualified Expression must match time type that is implied for expression by context" --- Quote End --- That is because you (and corestar) used "wait for". wait for expects a time expression, while rising_edge(clk) is a boolean expression based on a signal transition. You need to use "wait until", like in my example. --- Quote Start --- "Process statement must contain only one wait statement" --- Quote End --- Thats because you have tried to compile the code in Quartus - the quartus simulator will only simulate synthesisable code, and my code was definitely not synthesisable, only for testbenches. You need to run it in an RTL simulator, like modeslim.
