true dual port RAM

I didn't say it's a template, I say it follows the syntax rules. I particularly meant the way of registering respectively not registering addresses for read and write. I admit, that the Quartus Software Handbook doesn't explicitely show two write ports. But cause it's a feature of the hardware, the inference logic could be expected to understand it, too.

I didn't explicitely comment meaningless code details as

--- Quote Start ---

if wren_a='1' then

reg_rd_address_a <= address_a;

dpram_mem_trame(conv_integer(unsigned(address_a))) <= data_a;

else

reg_rd_address_a <= address_a;

end if;

--- Quote End ---

which is obviously equivalent to

--- Quote Start ---

if wren_a='1' then

dpram_mem_trame(conv_integer(unsigned(address_a))) <= data_a;

end if;

reg_rd_address_a <= address_a;

--- Quote End ---

I also didn't want to discuss if inference is reasonable in this case, just state that Quartus does understand it. (I actually tried, not just claim it). I agree, that it's not portable (may be to architectures with similar hardware features, but not based on well defined VHDL language constructs).

P.S.: I'm not an expert of general VHDL. (I guess you aren't, too). My main interest is in synthesizable code and corresponding simulation code. I notice however, that the VHDL language definition has effective means to define driver solution in different situations. They are also working in Quartus VHDL compiler without explicitely showing up. Thus I wouldn't say, that Quartus defines or uses it's own rules here. It apparently uses different rules than usual in assigning a signal to a register.