true dual port RAM

The code is perfectly inferring a dual-port RAM in Quartus. That can be expected, cause it's basically following the syntax suggested in the Quartus Software Handbook for MegaFunction inference from HDL code. Using a dual-port RAM is actually the only legal method to have two clocks and two drivers controlling a register bit, as the above code has.

Unfortunately ModelSim can't understand this special hardware prerequisites. This is probably the reason, why the RAM content is set to unknown. There may be a way to instruct ModelSim to understand the code, but I'm not aware of.

I generally share kaz opinion, that it's easier to explicitely instantiate an altsyncram MegaFunction. This can be done without using the MegaWizard, directly in your code and assures a correct handling by ModelSim. It's necessary anyway, if you need additional features as different port widths on both sides, that aren't supported in RAM inference.