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Altera_Forum's avatar
Altera_Forum
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16 years ago

true dual port RAM

Hello, I am trying to implement a true dual port RAM. It compiles on Quartus, and when I simulate it with a waveform, it works as I want. But when I try to run it on ModelSim Altera, output is u...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

You are writing to mem array on two clocks, one per each process. I don't see how this is going to work. You must decide the drive in one construct or else use Z assignments.

Moreover, your code doesn't look right to me even for inferring ordinary ram.

dual port ram is too difficult to infer - I believe. Why not use altera lpm