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Altera_Forum
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8 years ago

Trouble hardcoding an initial value of flip-flop on power up.

Hi All, I'm using a Max 10 FPGA. I'm having trouble instantiating a d flip flop initially set to '1'. From the altera.altera_primitives_components.all I am instantiating the following...
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Altera_Forum
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8 years ago

Consider that simultaneous asynchronous reset and preset isn't supported by MAX10 logic elements. It has to be emulated by a combination of DFF and combinational logic, including latches.

The dffeas primitive component and the ff wysiwyg component have a power_up generic, by the way.