tri-state bus inside FPGA.

Thank you for clarifying. I was erroneously assuming you're working with VHDL. VHDL would require to define explicite resolution functions for wired or, but it's actually a built-in Verilog feature.

I'm not aware of possible Quartus limitations in using wired net types across module boundaries. From the Verilog specification, it's clear that wired net types are intended to be connected through module ports, see e.g. the table "Net types resulting from dissimilar port connections".

I would try with a test code, that uses wor inside a module, and then extend it for multiple modules. Either there's a problem in your usage of the wired net constructs, or the claimed support is not valid for module ports.