tri-state bus inside FPGA.

gs_if(input clk, input rstn);
        wor          tx_data;
        logic          rx_data;
        logic          tx_addr;
        logic         rx_addr;
        logic                         wr;
        logic                 be;
endinterface
assign regs.tx_data = (ADDR == regs.tx_addr)?data:{64{1'b0}};