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Altera_Forum's avatar
Altera_Forum
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15 years ago

Tri-state buffer

Hi,

I had some question regarding the warning message below:

Warning: Tri-state node (s) do not directly drive top-level pin(s)

è Warning: Converted the fan-out from the tri-state buffer “tribuf” to the node “comb” into an OR gate

When I find the help message it state:

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Tri-state node(s) do not directly drive top-level pin(s)

CAUSE: The design contains tri-state nodes that drive non-tri-state logic, but the chip does not support internal tri-states. As a result, the Quartus II software converts all the tri-state nodes feeding internal logic to an equivalent logic.

For example, in the following design, the fan-out from the node tribuf to the AND gate is converted to an OR gate.

module test1 (input oe1, data1, in, output out, inout bidir);

wire tribuf, tmp;

assign tribuf = oe1 ? data1 : 1'bz;

and(tmp, in, tribuf);

assign bidir = tribuf;

assign out = tmp;

endmodule

ACTION: Avoid this warning by either removing the non-tri-state fan-outs of the affected tri-state nodes or replacing the tri-state nodes with non-tri-state logic.

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From the statement, it stated that it would convert the AND gate to the OR gate, however when used the Netlist-viewer->RTL-viewer for the tribuf, there is no OR gate converted. Where can I see the changes if the warning message had approached?

Thanks in advance for the help

Best regards

ken

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    If I understand correctly your question, you expect that the AND gate has been converted to an OR gate.

    Actually I think the warning simply states that an OR gate could be applied to the OUTPUT of the AND gate, but only if this signal (supposed to work as tristate) is connected in your system to other signals in a wired-or fashion.

    I suppose the OR gate is used to emulate the tristate behaviour in a physical device not supporting internal tristate lines. If your signal has a plain point to point connection, the or gate is not needed.

    Cris
  • Altera_Forum's avatar
    Altera_Forum
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    Dear Cris,

    Thanks for your reply,

    May be a diagram(tri-state) would better illustration the behavior, do you means by the signal below circle is understood that the OR gate is not needed?

    As since there is no “real” user-define name, they uses the names of one of its single tri-buffers as follow.

    warning: the following tri-state node(s) did not directly drive top-level pin(s)

    warning: converted the fanout from the tri-state buffer "inst" to the node "inst2" into an or gate

    Btw, how would be the equation below? Since it is using bidirectional for the first non-tri-state, would the equation still be inst + inst1 = inst2

    Thanks again

    Best regards

    ken
  • Altera_Forum's avatar
    Altera_Forum
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    I'm still not sure I understood what is your problem.

    Anyway the schematic confirms what I told you before.

    The TRI port is used to generate an internal signal but the device doesn't support internal tristate signals.

    Then I suppose that the compiler warns you that the TRI gate has been emulated through an OR function:

    TRI output = (not OE) or INPUT

    Regarding your final question, the equation is not valid. OPNDRN is a monodirectional gate (equivalent to a TRI with input connected to GND and oe connected to your input signal) even if it drives a bidir pin.

    In your schematic, output pin depends only on TRI gate output.

    Cris
  • Altera_Forum's avatar
    Altera_Forum
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    Dear Cris,

    I see what you mean now, Thank you very much. I really appreciate it. :)

    Best regards

    kenny