Traverse netlist with TimeQuest

It does not appear possible to traverse the netlist as I proposed. However I did come up with a workable solution for this problem (and Rysc independently came up with the same solution).

Add another LUT (LUT3) between LUT2 and LUT1 (only on the net driving LUT1, as the same output of LUT2 has other destinations where we do not want to disable timing). Then set_disable_timing on LUT3 without specifying input or output pins. This does add some delay on the total timing path, but since we're disabling timing anyway we don't care about the additional delay.

This solution has been tested and was sufficient for my application.