Transceivers in Stratix IV GT SI Development Board

Hi all,

I am using Quartus 13.0sp1. I am trying to include my code that generates two binary outputs using the clock signal as shown in simulation figure 1. My aim is now to send these outputs through the two separate transceivers. For that I updated the qsys file of the design example by removing the checker, generator and timing adapters and creating a new component from my code and incorporate that new component in the Qsys design. The above mentioned connections are shown in figure 2. When I generate my Qsys design file, it is generated without any errors. Now, in my instantiated verilog file, when I include the new Qsys design and compile the code, I get the following error( also included in Figure 3) .

Error: The internal TX PCS frequency and/or PLD clock limitation has been violated when the effective data rate has a value of '11300.0 Mbps' on the node 'link_test_sopc_sys_10g:link_test_sopc_sys_10g_inst|altera_xcvr_low_latency_phy:xcvr_low_latency_phy_0|siv_xcvr_low_latency_phy_nr:siv_xcvr_low_latency_phy_nr_inst|alt4gxb:pma_direct|alt4gxb_i1e9:auto_generated|ch_clk_div0'. The current TX channel settings are as follows: the Serializer divide-by factor has a value of '10', the Protocol Hint has a value of 'basic', the Use Double Data Mode has a value of 'false', the Basic low latency datapath mode has a value of 'true', the Enable PCI-Express Hard IP (HIP) has a value of 'false' on the node 'link_test_sopc_sys_10g:link_test_sopc_sys_10g_inst|altera_xcvr_low_latency_phy:xcvr_low_latency_phy_0|siv_xcvr_low_latency_phy_nr:siv_xcvr_low_latency_phy_nr_inst|alt4gxb:pma_direct|alt4gxb_i1e9:auto_generated|transmit_pcs0'.

Info: "600.0 Mbps to 2500.0 Mbps" is a legal range

Can any one help me on explaining the following error or any other way to transmit data via transceivers.