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Altera_Forum
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15 years ago

Top module logic utilization lesser than sub-modules

Just created a Verilog top-level module which instantiates about 10 sub-modules. When I wrote those individual sub-modules each of them took about 5%-6% of logic utilization. My estimate was that the...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

@jake, Thanks. Right now Quartus shows most of the submodules as synthesized away. But individually all the sub-modules when compiled as the top-level module show 6%-7% logic utilization. Would I be correct in inferring then that the problem doesn't lie in the definition of the sub-modules rather it is the issue of non-utilization of generated signals from the submodules in the top-level module?