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Altera_Forum
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15 years ago

Top module logic utilization lesser than sub-modules

Just created a Verilog top-level module which instantiates about 10 sub-modules. When I wrote those individual sub-modules each of them took about 5%-6% of logic utilization. My estimate was that the...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

You can look at the synthesis report to see what was synthesized away. Most common reasons for this are:

1 - You didn't connect the clock.

2 - You don't have any outputs dependent on the module outputs. If the logic of your modules to feed anything useful (like I/O) the whole thing gets optimized away. This happens all the time when people are trying to compile projects for size estimates.

Jake