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Altera_Forum
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15 years ago

Top module logic utilization lesser than sub-modules

Just created a Verilog top-level module which instantiates about 10 sub-modules. When I wrote those individual sub-modules each of them took about 5%-6% of logic utilization. My estimate was that the...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Thanks rbugalho, how can I see what modules are being optimized away. I guess that also means that I need to run simulations to find out what the bug in the top level module is and then fix the bug to see true logic utilization. However does anything come into your mind off the top of your head, because none of my submodules are custom, all are using altera floating point cores. Can you think of any signal(s) which might be causing them to be optimized away? Thanks again for your reply.