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Altera_Forum
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15 years ago

Top module logic utilization lesser than sub-modules

Just created a Verilog top-level module which instantiates about 10 sub-modules. When I wrote those individual sub-modules each of them took about 5%-6% of logic utilization. My estimate was that the...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

The tools are able to optimize each instance of each module.

And sometimes, minor bugs can cause modules to be optimized away almost entirely.

Ie, let's say that you have a submodule with a reset input.

Now let's say that you have a bug in your top level module that causes that submodule's reset signal to be a constant "1".

The tools will be, more or less, be able to see that and will reduce the submodule to almost nothing,