Forum Discussion
ShashwatS
New Contributor
New ContributorTop Level Design Error in my Verilog code
There is a "top level design" error in my Verilog code. Please mention some instructions to resolve this issue asap.
The code is for a C element in DMR
RichardT_altera
Super Contributor
Super ContributorAs sstrell mentioned, the top level entity name is mismatch with the module name.
To solve this, right-click the file and set it as Top-Level Entity.
Best Regards,
Richard Tan
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
