Forum Discussion
ShashwatS
New Contributor
New ContributorTop Level Design Error in my Verilog code
There is a "top level design" error in my Verilog code. Please mention some instructions to resolve this issue asap.
The code is for a C element in DMR
sstrell
Super Contributor
Super ContributorThe name you've specified as the top level entity in your Quartus project (celement) does not match the module name (c_element).
