Tool for VHDL/Verilog code documentation

I cant share because they are all protected company documents.

Usually, the document contains:

1. Reasons for the project

2. The interfaces used and why

3. The overall architecture and design functionality

4. Interface descriptions, including block to block port map, CPU register map etc.

5. Test plan, including the testbenches required, the tests required, and the hardware tests required.

6. The estimated resource usage

And this should all be written and reviewed before you write much/any HDL (obviously it should be updated as things change during the implementation, as they inevitably will)