Altera_Forum
Honored Contributor
13 years agotoo many sdc constraints?
Is there such a thing as too many sdc constraints. I ended up producing over 2000 multicycle
and false path constraints. my design fills a stratix V to 70%. And my main system clock is around 200MHz. I wanted to know if quartus execution time will suffer due this. I will kick off a run to find out but wanted to get a heads up from anyone whos been there.