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Thanks guys, I can't test right now if that will work cause I'm not on my laptop, but I believe so.
Actually doesn't matter the pins, cause I will call this *.VHD as a component (label, port map. Sorry I don't know how it's really called) and this new file will direct the data for each one of the first file pins. Maybe I could use even signals as i/o since it's not real i/o pins, but I don't know if it's possible.
I will test your tips soon.
Appreciate the help.
Thank You!
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you wouldnt be able to connect them to dangling signals, because the synthesisor will just see them as not connected to top level IO and synthesise them all away (and your entire design).
You can do a workaround if you dont have the subscription edition. Just run all of the component ios through some logic gates (like ands and ors and stuff) and then connect them to top level IO - this will prevent them from being synthesised away.
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