Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Timing Violations workaround strategy

Hello, Probably I didn't properly define timing constraints ... TimeQuest reported quite a lot of timing violations. In this connection I have one question - does exist some straightforward a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

I use all timing constraints in every synthesis run (not just for timing analysis with Timequest). Finding the right ones it's an iterative process. Before you can run Timequest you have to do a complete fit. First I assign basic constraints (base clocks, virtual clocks, I/O delays, derive_pll_clocks, derive_clock_uncertainty, set_clock_groups)

The virtual clocks are for I/O timing analysis, please refer TimeQuest Timing Analyzer Cookbook (MNL-01035 2016.2.25, page 9)

Jens