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Pavel, you are rigth constrain timing is an iterative process
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So, you confirm that when you start working on your project (i.e. design is accomplished in Quartus/Qsys, but isn't compiled yet), you have no any idea how how design will be fit during compilation.
Consequently you can't apply any "hard" constraints (e.g. multicycling), but only the very basic ones (i.e. creating clocks), isn't it ?
That's why I was surprised when you said that you apply "multicycling" constraint "at once" (i.e. without preliminary compilation or TimeQuest run).
Or I misunderstood your approach ?
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No the SDRAM is clocked from the FPGA. As I wrote the clock does not drive any internal logic but it comes from an internal PLL.
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If you have no any additional clocks on your board (except basic clock), what sense to create virtual clock ?
In all manuals virtual clock is created to "emulate" some external clock.
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This virtual clock is used to constrain the I/O timing like:
set_output_delay -max $SDRAM_MAX_OUT_DELAY -clock virt_100MHz_clk [get_ports SD_DATA*]
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Why not use PLL-generated clock for this ?
Honored Contributor
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