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Altera_Forum
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8 years ago

Timing Violations workaround strategy

Hello, Probably I didn't properly define timing constraints ... TimeQuest reported quite a lot of timing violations. In this connection I have one question - does exist some straightforward a...
Altera_Forum's avatar
Altera_Forum
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8 years ago

Pavel, you are rigth constrain timing is an iterative process.

No the SDRAM is clocked from the FPGA. As I wrote the clock does not drive any internal logic but it comes from an internal PLL.

This virtual clock is used to constrain the I/O timing like:

set_output_delay -max $SDRAM_MAX_OUT_DELAY -clock virt_100MHz_clk [get_ports SD_DATA*]

Jens