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Altera_Forum
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8 years ago

Timing Violations workaround strategy

Hello, Probably I didn't properly define timing constraints ... TimeQuest reported quite a lot of timing violations. In this connection I have one question - does exist some straightforward a...
Altera_Forum's avatar
Altera_Forum
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8 years ago

1. If you look at the fitter messages you can see something like this:

"Info (332104): Reading SDC File: 'project_timing.sdc'"

I think fitter use constraints for controlling desing optimization.

2. The virtual clock is just used outside the FPGA. No internal logic is driven from this clock but it's from the PLL inside.

3. Yes I do. Sometimes it works. But if you want closure timing than you have to use the rigth constraints.

Jens