Timing Violations workaround strategy

Hi Pavel,

1. Yes at once becaus the fitter is using timing constraints.

2. It's the virtual clock for the I/O timing analysis (see Quartus II Handbook, QII5V3 2015.05.04. p. 7-14 or the TimeQuest User guide from Ryan Scoville, http://www.alterawiki.com/wiki/timequest_user_guide)

3. No, I use the shift calculated according the Embedded Peripherals IP User Guide

Do you drive the internal sdram_controller with the same clock as the external SDRAM device? The external clocks should be shifted. In your screenshot the launch clock should be the external shifted clock and the latch clock is the internal clock. The multicycle -setup constraint is used to tell Timequest what is the right latch edge.