Timing Violations workaround strategy

Hi Jens,

A couple of questions:

1. Did you apply multicycle constraint at once ... or after running TimeQuest (and analyzing results) at least one time ?

2. What is virt_100mhz_clk? Is it external clock or PLL-generated clock ?

3. Did you try to workaround timing violations by tuning the phase shift between "sdram clock" and "sdram controller clock" ?

Thanks

P.S. I've just run timing analysis without multi-cycle constraint, but applying phase shift between 2 PLL-generated clocks (according to approach from embedded peripherals ip user guide, pp. 2-10 ... 2-14).

Also I applied input and output constraints calculating them according to "demystifying timing constraints" from your link.

Here is the content of my .SDC file:

create_clock -name clk -period 20 create_clock -name {altera_reserved_tck} -period 40 {altera_reserved_tck}
derive_pll_clocks
derive_clock_uncertainty
set_input_delay -clock altera_reserved_tck -clock_fall 3 
set_input_delay -clock altera_reserved_tck -clock_fall 3 
set_output_delay -clock altera_reserved_tck 3 
create_generated_clock -name clk_ext_sdram -source .gpll~PLL_OUTPUT_COUNTER|divclk}] 
#  Constraint SDRAM DATA for input
set_input_delay -clock clk_ext_sdram -max 6.4 ]
set_input_delay -clock clk_ext_sdram -min 1.0 ]
#  Constraint SDRAM DATA for output
set_output_delay -clock clk_ext_sdram -max 1.5 
set_output_delay -clock clk_ext_sdram -min -0.8 
set_multicycle_path -setup -to }] 2# set_multicycle_path -hold -to }] 1
set_false_path -from 
set_false_path -from 
set_false_path -from * -to 
set_false_path -from * -to 

The 1st location where I consult timing violations is "Report all I/O Timings".

There are 16 timing HOLD violations (related to SDRAM data) and 55 SETUP violations (related to all (at 1st glance) SDRAM ports).

Surprisingly launch clock and latch clock are the same. Any comments.

Thanks.

Here is screenshot for HOLD violations.

https://alteraforum.com/forum/attachment.php?attachmentid=13664&stc=1