Timing Violations workaround strategy

I'm using a SDRAM at 100 MHz clock whit the SDRAM controller in QSYS (altera_avalon_new_sdram_controller). For calculation the shift between the controller clock and the external clock I used the Embedded Peripherals IP User Guide (UG-01085 2016.12.19, page 2-10).

In the .sdc I defined a setup multicycle for shifting the window:

set_multicycle_path -from [get_clocks SOPC|sys_pll|clk_100] -to [get_clocks virt_100MHz_clk] -setup 2

These clock groups must related in timequest, do not use set_clock_groups -asynchronous/ -exclusive.

Here you is a good guidance for this toic:

http://retroramblings.net/?p=515

regards

Jens