Timing Violations workaround strategy

Looking at the path for the clock going out to SDRAM and data coming back. Let's start with the case where you use the same clock to launch and latch the data, so there is a 0ns hold relationship and 7.5ns setup. Let's say the external delay -max and -min are both 0ns. If you compile and your setup slack is 1ns and your hold slack is 3ns. To think of what's going on, let's say the clock skew is 0 inside the FPGA. (This is weird, as the clock feeds the latch register, but it doesn't feed an actual launch register. Let's just say it's the output register). Anyway, by having 1ns of setup slack, it means the clock got out through the output buffer and came back in through the data input buffer and to the register in 6.5ns. So your max data delay is 6.5ns.

By having 3ns of hold slack, we're saying this same delay in the Fast Timing Model was 3ns.

Of course, your external delay is not 0ns. Let's say the SDRAM's TCO has a max of 8ns and min of 4ns. So if you change the external delays to this, with the same fit, you would end up with setup slack of -7ns and hold slack of 7ns.

So we're missing timing by a lot. You could add a multicycle setup of 2 and multicycle hold of 1, so that your now trying to latch on the next falling edge at time 15ns, e.g. when a clock edge comes in at time 0ns, it will go out of the FPGA to the SDRAM, have data come back, and you'll latch that at time 15ns. You will also have a positive hold relationship of 7.5ns, meaning that whole delay must be greater than 7.5ns.

Since your FPGA delay was 6ns and you added 8ns for the external delay, the total is 14ns and your actually making setup. But your fastest delay is 7ns and you need it to be 7.5ns. THis is where it gets tricky, as the fitter can turn up delay chains/routing to try and meet hold. But let's say it adds 0.75ns of delay and now it's meeting hold in the Fast Corner. As a general rule of thumb, I say the slow corner is 2x the Fast Corner, so this would add 1.5ns of delay to the slowest delay, e.g the FPGA data path becomes 6+1.5=7.5ns and then with the 8ns external delay you're now failing setup rlationship 15ns.

This is just an example, but you do need to figure out the external delays because I don't know if you're in the right ballpark of whether this is feasible, as 150MHz is pretty fast for SDRAM interface.

Now, it may be that you don't read on every cycle, e.g. it may be every other cycle at best. In that case, your setup relatinoship could be 15ns but your hold could be 0ns, in which case the fitter would never need to add delay to meet hold timing, as it would automatically meet the hold.