Timing Violations workaround strategy

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Do you mean my 2nd message on this thread ?

The design was modified since that moment ... e.g. 2 PLL outputs became in phase.

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I meant this last post from you:

Report Timing HOLD "to clock" clk_ext_sdram

It could be the clk_ext_sdram is latching e.g. m_dq to sdram_dq internally then sending it to sdram. But I thought you have defined clk_ext_sdram as generated output clock.