Timing Violations workaround strategy

I would have thought that io failed hold time based on my reading in your second report as it is launch by divclk but latch by clk_ext_sdram.

So how could io report pass with no failure. Obviously I am mis-reading your reports. You are in a position to identify if io paths are ok. If so no need fr phase shift and your focus should be on the design. issues like using fitter settings, pipelining if available...I know it is qsys generated stuff but you can manipulate settings.