Timing Violations workaround strategy

You better run TimeQuest GUI and check all failing paths and io paths.

Your setup report seems about internal paths [launch and latch are divclk] but your hold report is io path which shows some negative slack.

You need to check setup for io paths as well. Both inputs and output io paths need to be reported.

If io paths are failing you can use some phase shift to help it out [you can experiment on that].

For internal paths on 150MHz that is a design issue and basically 150MHz should not be a problem in many fpgas. But it is not clear why this failure occurs.