Here is TimeQuest results with no phase shift between 2 PLL-derived clocks:
- 1st clcok clocks all Qsys modules (including SDRAM controller)
- 2nd clock clocks external SDRAM chip
Here is screenshot from 3 Qsys reports (hope that it will be published immediately, without n-hours pending/approving):
- Report Clocks
- Report Timing SETUP "to clock" u0|pll|altera_pll_i|general
- Report Timing HOLD "to clock" clk_ext_sdram
Surprisingly, in the "Report Clocks" there are only 1 PLL-generated clock, whereas I set 2 PLL outputs in Qsys
https://www.alteraforum.com/forum/attachment.php?attachmentid=13603
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