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Honored Contributor
Honored ContributorTiming Violations workaround strategy
Hello, Probably I didn't properly define timing constraints ... TimeQuest reported quite a lot of timing violations. In this connection I have one question - does exist some straightforward a...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- No, according to SDRAM datasheet, it's clocked on positive edge. So, you propose to remove phase shift on u0|pll|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk and consequently on clk_ext_sdram ? --- Quote End --- For an SDR interface try first same phase and if you get into trouble then play with the phase.
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