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But you are latching it on divclk: is it also 150MHz and then why have you changed its phase.
Although this clock of clk_ext_sdram is opposte data input but that is a trivial issue for now...
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Yes, data that comes into FPGA (SDRAM controller IP to be precise) is
latched by u0|pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk (which is PLL-derived clock with 0 phase shift).
And the data
launch clock is PLL-derived clock with
-3.5ns phase shift, so the
launch clock is about
half-period "advanced" with respect to
latch clock and respectively the
latch clocks is
half-period delayed with respect to
launch clock. Correct ?
Probably this half-period shift is intended to account for board propagation delay ?
Anyway, if I properly understood, you propose to remove phase shift in launch clock. Correct ?
Honored Contributor
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