Timing Violations workaround strategy

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You mean why external sdram memory chip isn't clocked with the same clock as internal sdram controller ? This clocking schema I've picked from a reference design that was in support board package. By the way there was no any constraints on SDRAM interface I/O in the .sdc file.

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You are sending a clock to sdram chip as you have done (isn't it the clk_ext_sdram as named in your sdc). That is ok

I am referring to your sdc constrains of set_input_delay/set_output_delay for sdram_dq.

You are telling Timequest that sdram_dq data is clocked out from sdram chip on clk_ext_sdram. That is ok

But you are latching it on divclk: is it also 150MHz and then why have you changed its phase.

Although this clock of clk_ext_sdram is opposte data input but that is a trivial issue for now...