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Honored Contributor
Honored ContributorTiming Violations workaround strategy
Hello, Probably I didn't properly define timing constraints ... TimeQuest reported quite a lot of timing violations. In this connection I have one question - does exist some straightforward a...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- The failed paths (if inputs to fpga) are clocked out by clk_ext_sdram according to sdc but are latched on divclk. This has resulted in a setup relationship of 3.5 instead of 6.667 and is the root cause of problem. Why not latch input with same clock as sdram clock --- Quote End --- You mean why external sdram memory chip isn't clocked with the same clock as internal sdram controller ? This clocking schema I've picked from a reference design that was in support board package. By the way there was no any constraints on SDRAM interface I/O in the .sdc file.
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