Timing Violations workaround strategy

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So the clock you're using for the input constraint is the clock you're sending out.

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For gpios I use false_path, as timing is non relevant for buttons, switches, LEDs.

Input/output contraints I applied only for sdram interface

Yes, I use clock that goes out for input constraints (sdram data) and also for output constraints (all sdram signals - data/address/controls).

This clock is derived from pll and its frequency is 150 MHz (3 times input external frequency). It's also -3.5ns shifted.

There is also another PLL-derived clock that clocks SDRAM controller. It's frequency is also 150MHz, but as opposed to the first one, it isn't shifted.

The SDRAM controller is responsible for generating all SDRAM interface signals - data, address, control signals.

As I've already mentioned previously I'm not sure that it's the optimal solution, I've just picked it from reference design.

So, let's resume:

• clock, used for input/output constraints is 150MHz, and has shift -3.5ns

• input/output signals are formed in SDRAM controller that is clocked by the 150MHz 0-shifted clock

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I assume the clock goes out and data comes back in.

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For clock - Yes, it goes out. For data - both directions ... i.e. data goes out and data comes in. It's cpu nios ii, that communicates with sdram and certainly necessitate data transfer in both directions (that's why I applied 2 types of constraints for sdram data bus - set_input_delay and setup_output_delay)

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So the -max and -min values would represent the max and min external roundtrip delay from clock going out to data coming back in. I would plug those values in, as they're going to be large and their variation will determine if this is possible.

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Here I didn't properly understand what you mean. Could you, please, develop a little more this issue.

Concerning these -max and -min values ... they are made up from (1) track delays and (2) external device setup. So, ideally, one can set these values at once ... (1) by examining board layout and calculating track delay (rough estimation - using simplified electromagnetic formulas, or fine estimation, using electromagnetic simulators (e.g. mentor graphics hyperlynx, ansys electromagnetics, cst studio, etc.) and (2) examining external device datasheet ?

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After that's done, you will probably have to change the phase-shift, and most likely will need a multicycle since the data will be coming back more than one clock cycle after it was sent. I am worried about min/max variatino being too large, but we'll see.

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You mean change phase-shift in PLL settings for 2nd output ? ... and apply multicycle constraints to all sdram interface (i.e. data/address/controls) ?

But, Ok, it will become perhaps more clear once I understand the previous point.

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Does the SDRAM read data at full rate, e.g. every clock that goes out you expect new data to come back, or is it slower?

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I don't think so. Since it's cpu nios ii, that handles data transfer from/to sdram, there are probably "silent" periods, when there are no data transfer at all, e.g. CPU process the data that are already in CPU internal registers.

Thanks once more.