Timing Violations workaround strategy

Can you give more details? At first I assumed this was a regular input constraint, since the From Node appears to be a pin and the clock is external. But the Launch Clock path at the bottom starts at Pin AF14 and goes through the FPGA, where usually an external clock "just exists" and has no dependency on the delays inside the FPGA.

Second, the clock appears to be phase-shifted from each other, where the latch clock's falling edge occurs shortly after the launch edge. This results in a 3.5ns setup relationship but the clock period is probably closer to 7ns or something like that. Where does this clock relationship come from? (I don't just mean "I put a phase-shift on the PLL", but in laymen's terms, just describe the interface, e.g. what the clock rates are, what the external delays relationships are, etc.)

The reason a multicycle is unlikely to work is that the hold time gets pushed out too. In this case it would be 3.5ns. So in the fast corner the data delay would be 3.5ns, and as a quick rule of thumb I assume the slow corner is 2x the fast corner, meaning the delay would be at least 7ns. Actually, this might meet the new setup, but it's somewhat tight. So it might be possible.

There are no recipes or formulas that work all the time. They key is understanding what analysis you're doing and how it relates to the hardware. If that doesn't make sense, you can never be sure about any solution. Anyway, please provide more info about what's going on.