--- Quote Start ---
The PLL module in Qsys has 2 ouput and one of them is phase-shifted. This phase shift isn't reflected in .SDC file ... I beleived that TimeQuest can handle this shift without .SDC modification (again probably I'm wrong)
--- Quote End ---
Yes, if you use derive_pll_clocks coammand PLL clocks are created automaticaly with correct parameters. You can check that in "Report Clocks".
--- Quote Start ---
So even in this case multicycles can't be considered as "reliable remedy"
--- Quote End ---
With multicycle exception you are only telling for TimeQuest how your design works. For example:
- for paths requiring more than one cycle for data to propagate you should apply multicycle path exception to "open the Window".
[LIST]
In some cases when TimeQuest does not properly detect launch and latch edges multicycle exception is used to properly define launch and latch edges ("shifting the window" for phase-shifted clocks).
[/LIST]
Multicycle exception can solve timing violations caused by incorrect timing analysis (wrong launch and lath edge relationship ect.), but multicycles can't be considered as remedy for any REAL timing violation. If you apply multicycle exception but your design does not work like that timing analysis will be incorrect.
Provide clock report, clock transfer report, and detailed failing path report
Honored Contributor
.jpg){kind=link}