Timing Violations workaround strategy

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Probably I didn't properly define timing constraints ... TimeQuest reported quite a lot of timing violations.

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1. Check if there are any ignored constrains.

2. Check if there are any unconstrained paths.

3. Check clock transfers and make sure that there are no invalid clock transfers analysed.

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Does exist some straightforward approach on working around "timing violations" ?

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It depends what causes those timing violations.

Violations between unrelated clocks or paths - usually can be solved by setting clock groups or setting false path between unrelated paths.

Violations in register-to-register level - usually caused by bad coding style, go back to your VHDL/Verilog code and fix it.

Violations in I/O - can be solved by using PLL and clock phase shift, clock inversion ect.