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FabianL's avatar
FabianL
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8 months ago
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Timing Violations in JTAG Signals

Hello, I have a Arria10 FPGA design using Platform Desginer which includes a Avalon to JTAG Brdige. I have added a jtag.sdc file to the project based on this guideline: JTAG Signals and set all th...
  • KennyT_altera's avatar
    6 months ago

    After internal testing and discussion, we’ve confirmed the following for Arria 10 devices:

    • Only the on-board USB-Blaster II is capable of supporting up to 24 MHz.
    • The off-board USB-Blaster II cannot reach 24 MHz due to certain limitations
    • That said, if the TDO pin of the Arria 10 is driving the TDI of another device through a short trace, it can still support up to 24 MHz.

    In the SDC files, you’ll notice a placeholder such as <<customer here>>. This needs to be updated based on the actual trace length measurements on your board. If you're targeting 24 MHz, the timing constraints will need to be tighter to meet the higher frequency requirements.

    I'll attach a sample SDC file that helps close timing at higher speeds. Let me know if you have any further questions.