Timing violation with Altera GPIO in DDR mode

Hi,

at the moment I'm trying to get the best timing of our hardware, so I use the gpio instead of PhyLite. There I have a routing problem. I used logiclock regions and design partitions to fix the routing.

I set small logiclock regions in front of the ADC pins, the registers after the pins were placed inside the logiclock region, but the pysical routing seems to be strange as you can see on the picture.

There is a negative setup slack on this path. But the hold slack don't need to be that good as it is.

I also added a qar archive.

Can you tell me why the router routes this long way?

Thank you.