Timing violation with Altera GPIO in DDR mode

​Hi,

I tried Phy Lite but had problems with setting the correct frequencies as I wrote 19 days before.

The text was:

In the handbook Intel recommends to use PHYLite for source synchronous Interfaces with more than 200 Mbps.

I set the Interface clock to 262.144MHz, clock rate of user logic: Full

If I do so, I cannot set the PLL reference clock to 262.144MHz. Just half of it, but I need to set this clock, because it is coming from the ADC.

I don't know why it is not possible. In the PHYLite User Guide

https://www.intel.com/content/www/us/en/programmable/documentation/bhc1410942178562.html#bhc1410941851660/en-us Table 3

the Max Core Clock Rate (Full) with Arria 10 Speed Grade -2 is 266MHz.

Thanks.