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MRenn's avatar
MRenn
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6 years ago

Timing violation with Altera GPIO in DDR mode

I have a setup violation at the register after the input register. The input register is constrained as described in AN433. set_input_delay -add_delay -clock virt_adc_clk -min -0.6 [get...
MRenn's avatar
MRenn
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6 years ago

Now I tested with 18.1. The Timing is the same, also slacks with setup and hold.