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MRenn
New Contributor
New ContributorTiming violation with Altera GPIO in DDR mode
I have a setup violation at the register after the input register. The input register is constrained as described in AN433. set_input_delay -add_delay -clock virt_adc_clk -min -0.6 [get...
MRennNew Contributor
New ContributorHi,
because of this issue we still use Quartus Prime 16.1.1 Build 200
https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/ip/2019/why-is-the-last-output-frame-of-the-intel--fft-ip-core-missing-e.html
I manually added the qpf and qsf to the archive.
Thank you for your help.
