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MRenn's avatar
MRenn
Icon for New Contributor rankNew Contributor
6 years ago

Timing violation with Altera GPIO in DDR mode

I have a setup violation at the register after the input register. The input register is constrained as described in AN433. set_input_delay -add_delay -clock virt_adc_clk -min -0.6 [get...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
6 years ago

Yes, get rid of create_base_clocks unless with "I thought I need it forc other PPLs." you mean that you have other PLLs in your design that are sourced from other input reference clocks. I'd still manually create all the base clocks, though.

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