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MRenn
New Contributor
New ContributorTiming violation with Altera GPIO in DDR mode
I have a setup violation at the register after the input register. The input register is constrained as described in AN433. set_input_delay -add_delay -clock virt_adc_clk -min -0.6 [get...
sstrell
Super Contributor
Super ContributorGet rid of the generated clock constraint. derive_pll_clocks does that for you. Also, is this edge-aligned or center-aligned? Instead of using -create_base_clocks, you need to have a create_clock constraint that properly defines the relationship between the virtual clock and the clock coming into the FPGA depending on that alignment using the -waveform option.
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